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general description the max1217 dual, monolithic, 12-bit, 125msps analog- to-digital converter (adc) provides outstanding dynam- ic performance up to a 250mhz input frequency. the device operates with conversion rates up to 125msps while consuming only 650mw per channel. at 125msps and an input frequency of 200mhz, the max1217 achieves an 80dbc spurious-free dynamic range (sfdr) with excellent 65.3db signal-to-noise ratio (snr) at 200mhz. the snr remains flat (within 3db) for input tones up to 200mhz. this makes the max1217 ideal for wideband applications such as communications receivers, cable head-end receivers, and power-amplifi- er predistortion in cellular base-station transceivers. the max1217 operates from a single 1.8v power sup- ply. the analog inputs of each channel are designed for ac-coupled, differential or single-ended operation. the adc also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 250mhz and reduces the phase noise of the input clock source. a low-voltage differential signal (lvds) sampling clock is recommended for best performance. the converter? digital outputs are lvds compatible and the data format can be selected to be either two? complement or offset binary. the max1217 is available in a 100-pin tqfp package with exposed paddle and is specified over the extend- ed (-40? to +85?) temperature range. refer to the max1218 (170msps) and the max1219 (210msps) data sheets for higher speed, pin-compatible devices. applications cable modem termination systems (cmts) cable digital return path transmitters cellular base-station power-amplifier linearization if and baseband digitization ate and instrumentation radar systems features 125msps conversion rate excellent low-noise characteristics snr = 67db at f in = 100mhz snr = 65.3db at f in = 200mhz excellent dynamic range sfdr = 85dbc at f in = 100mhz sfdr = 80dbc at f in = 200mhz single 1.8v supply 1.3w power dissipation at f sample = 125msps and f in = 10mhz on-chip track-and-hold amplifier internal 1.24v bandgap reference on-chip selectable divide-by-2 clock input lvds digital outputs with data clock output ev kit available (order max1217evkit) max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ________________________________________________________________ maxim integrated products 1 part temp range pin-package pkg code max1217ecq -40 c to +85 c 100 tqfp-ep* c100e-6 pin-compatible versions ordering information part resolution (bits) speed grade (msps) max1219 12 210 max1218 12 170 max1217 12 125 19-3759; rev 0; 8/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configuration appears at end of data sheet. * ep = exposed paddle.
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (av cc = ov cc = +1.8v, agnd = ognd = 0, f sample = 125mhz, differential input and differential sine-wave clock signal, 0.1? capacitors on refa and refb, internal reference, digital output differential r l = 100 , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to agnd ......................................................-0.3v to +2.1v ov cc to ognd .....................................................-0.3v to +2.1v ov cc to av cc .......................................................-0.3v to +0.3v ognd to agnd ....................................................-0.3v to +0.3v clkp, clkn, inap, inan, inbp, inbn to agnd .....................................-0.3v to (av cc + 0.3v) clkdiv, t /ba, t /bb to agnd .................-0.3v to (av cc + 0.3v) refa, refadja, refb, refadjb to agnd...............................................-0.3v to (av cc + 0.3v) dcop, dcon, da0p?a11p, da0n?a11n, db0p?b11p, db0n?b11n, orap, oran, orbp, orbn to ognd .......................-0.3v to (ov cc + 0.3v) current into any pin.............................................................50ma esd voltage on inap, inan, inbp, inbn (human body model).....................................................?50v esd voltage on all other pins (human body model)......?000v continuous power dissipation (t a = +70?) 100-pin tqfp (derate 37mw/? above +70?).........2963mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution n 12 bits integral nonlinearity (note 2) inl f in = 10mhz -2 ?.6 +2 lsb differential nonlinearity (note 2) dnl no missing codes -1 ?.3 +1 lsb transfer curve offset v os t a = +25? (note 2) -3 +3 mv offset temperature drift 10 ?/? analog inputs (inap, inan, inbp, inbn) full-scale input voltage range v fsr t a = +25? (note 2) 1375 1475 1625 mv p-p full-scale range temperature drift 150 ppm/? common-mode input range v cm 0.8 v differential input capacitance c in 3pf differential input resistance r in 1.8 k full-power analog bandwidth fpbw 800 mhz reference (refa, refb, refadja, refadjb) reference output voltage v ref_ t a = +25?, refadj_ = agnd 1.18 1.24 1.30 v reference temperature drift 65 ppm/? refadj_ input high voltage v refadj_ used to disable the internal reference av cc - 0.1 v sampling characteristics maximum sampling rate f sample 125 mhz minimum sampling rate f sample 40 mhz
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (av cc = ov cc = +1.8v, agnd = ognd = 0, f sample = 125mhz, differential input and differential sine-wave clock signal, 0.1? capacitors on refa and refb, internal reference, digital output differential r l = 100 , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units clock pulse-width low t cl figure 5 (note 3) 2 20 ns clock pulse-width high t ch figure 5 (note 3) 2 20 ns clock duty cycle set by clock-management circuit 40 to 60 % aperture delay t ad figures 5, 11 340 ps aperture jitter t aj figure 11 0.15 ps rms clock inputs (clkp, clkn) differential clock input amplitude (note 3) 200 500 mv p-p clock input common-mode voltage v clkcm 1.15 ?0.25 v clock differential input resistance r clk t a = +25? (note 3) 10 ?5% k clock differential input capacitance c clk 3pf dynamic characteristics (at -1dbfs) (note 4) f in = 10mhz 65.2 67.7 f in = 65mhz 65.2 67.5 f in = 100mhz 67 signal-to-noise ratio snr f in = 200mhz 65.3 db f in = 10mhz 10.5 11 f in = 65mhz 10.5 10.9 f in = 100mhz 10.8 effective number of bits enob f in = 200mhz 10.6 bits f in = 10mhz 65 67.6 f in = 65mhz 65 67.4 f in = 100mhz 66.8 signal-to-noise plus distortion sinad f in = 200mhz 65.1 db f in = 10mhz 72 88 f in = 65mhz 72 86 f in = 100mhz 85 spurious-free dynamic range sfdr f in = 200mhz 80 dbc f in = 10mhz -88 -72 f in = 65mhz -86 -72 f in = 100mhz -85 worst harmonic (hd2 or hd3) f in = 200mhz -80 dbc f in1 = 29mhz at -7dbfs f in2 = 31mhz at -7dbfs -92 two-tone intermodulation distortion ttimd f in1 = 97mhz at -7dbfs f in2 = 100mhz at -7dbfs -90 dbc
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 4 _______________________________________________________________________________________ dc electrical characteristics (continued) (av cc = ov cc = +1.8v, agnd = ognd = 0, f sample = 125mhz, differential input and differential sine-wave clock signal, 0.1? capacitors on refa and refb, internal reference, digital output differential r l = 100 , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units channel crosstalk and channel matching specifications channel isolation f in = 200mhz, a in = -1dbfs 90 db lvcmos logic inputs (clkdiv, t /ba, t /bb) input high voltage v ih 0.8 x ov cc v input low voltage v il 0.2 x ov cc v input capacitance 2pf lvds digital outputs (da0p/n?a11p/n, db0p/n?b11p/n, orap/n, orbp/n, dcop/n) differential output voltage |v od | 225 490 mv output offset voltage v os 1.125 1.310 v output timing characteristics clk to data propagation delay t pdl figure 5 (note 3) 1.7 ns clk to dco propagation delay t cpdl figure 5 (note 3) 5.2 ns dco to data propagation delay t pdl - t cpdl (note 3) 3.7 4.4 5.2 ns lvds output rise time t rl 20% to 80%, c l = 5pf 350 ps lvds output fall time t fl 20% to 80%, c l = 5pf 350 ps output data pipeline delay t latency figure 5 11 clock cycles power requirements analog supply voltage range av cc 1.71 1.8 1.89 v output supply voltage range ov cc 1.71 1.8 1.89 v analog supply current i avcc f in = 10mhz 600 725 ma output supply current i ovcc f in = 10mhz 120 160 ma analog power dissipation p diss f in = 10mhz 1.3 1.6 w power-supply rejection ratio psrr (note 5) 1 mv/v note 1: values at t a = +25? to +85? are guaranteed by production test. values at t a < +25? are guaranteed by design and characterization. note 2: static linearity and offset parameters are computed from a best-fit straight line through the code transition points. the full-scale range (fsr) is defined as 4095 x slope of the line. note 3: parameter guaranteed by design and characterization; t a = -40? to +85?. note 4: enob and sinad are computed from a curve fit. note 5: psrr is measured with the analog and output supplies connected to the same potential.
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications _______________________________________________________________________________________ 5 typical operating characteristics (av cc = ov cc = +1.8v, f sample = 125mhz, differential input and differential sine-wave clock, 0.1? capacitors on refa and refb, digital output differential r l = 100 , t a = +25?, unless otherwise noted.) -110 -90 -100 -60 -70 -80 -50 -40 -20 -10 -30 0 fft plot (16,384 samples) max1217 toc01 frequency (mhz) amplitude (db) f in = 12.4893188mhz f sample = 125mhz a in = -0.959dbfs sinad = 67.778db snr = 67.9db thd = -83.336dbc sfdr = 86.372dbc hd2 = -86.372dbc hd3 = -88.968dbc 0102030405060 10 9 8 2 7 4, 6 5 3 -110 -90 -100 -60 -70 -80 -50 -40 -20 -10 -30 0 fft plot (16,384 samples) max1217 toc02 frequency (mhz) amplitude (db) f in = 65.0100708mhz f sample = 125mhz a in = -1.001dbfs sinad = 67.416db snr = 67.514db thd = -83.914dbc sfdr = 88.662dbc hd2 = -89.221dbc hd3 = -88.662dbc 0102030405060 10 4 6 8 2 5 3 7 9 -110 -90 -100 -60 -70 -80 -50 -40 -20 -10 -30 0 fft plot (16,384 samples) max1217 toc03 frequency (mhz) amplitude (db) f in = 100.4867554mhz f sample = 125mhz a in = -1.092dbfs sinad = 66.84db snr = 66.966db thd = -82.247dbc sfdr = 85.865dbc hd2 = -87.081dbc hd3 = -85.865dbc 0102030405060 10 4 9 5 2 3 6 7 -110 -90 -100 -60 -70 -80 -50 -40 -20 -10 -30 0 fft plot (16,384 samples) max1217 toc04 frequency (mhz) amplitude (db) f in = 200.5996704mhz f sample = 125mhz a in = -0.992dbfs sinad = 65.098db snr = 65.341db thd = -77.742dbc sfdr = 80.122dbc hd2 = -82.718dbc hd3 = -80.122dbc 0102030405060 10 3 2 5 7 9 4 8 6 -110 -100 -105 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 hd2/hd3 vs. analog input frequency (f sample = 125mhz, a in = -1dbfs) max1217 toc07 analog input frequency (mhz) hd2/hd3 (dbc) 0100 50 150 200 250 hd3 hd2 -110 -90 -100 -60 -70 -80 -50 -40 -20 -10 -30 0 fft plot (16,384 samples) max1217 toc05 frequency (mhz) amplitude (db) f in = 251.3046265mhz f sample = 125mhz a in = -1.066dbfs sinad = 64.153db snr = 64.484db thd = -75.496dbc sfdr = 78.786dbc hd2 = -78.977dbc hd3 = -78.786dbc 0102030405060 4 2 3 7 6 9 8 10 5 snr/sinad vs. analog input frequency (f sample = 125mhz, a in = -1dbfs) max1217 toc06 analog input frequency (mhz) snr/sinad (db) 58 61 64 67 70 55 0 50 100 150 200 250 snr sinad 50 65 60 55 70 75 80 85 90 95 100 0100 50 150 200 250 sfdr/(-thd) vs. analog input frequency (f sample = 125mhz, a in = -1dbfs) max1217 toc08 analog input frequency (mhz) sfdr/(-thd) (dbc) sfdr -thd 50 70 68 66 64 62 60 58 56 54 52 72 20 50 80 snr/sinad vs. f sample (f in = 65.010071mhz, a in = -1dbfs) max1217 toc09 f sample (mhz) snr/sinad (db) 65 35 95 110 125 sinad snr
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av cc = ov cc = +1.8v, f sample = 125mhz, differential input and differential sine-wave clock, 0.1? capacitors on refa and refb, digital output differential r l = 100 , t a = +25?, unless otherwise noted.) -110 -100 -105 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 20 50 80 110 hd2/hd3 vs. f sample (f in = 65.010071mhz, a in = -1dbfs) max1217 toc10 f sample (mhz) hd2/hd3 (dbc) 65 35 95 125 hd3 hd2 50 60 55 70 65 80 75 85 95 90 100 sfdr/(-thd) vs. f sample (f in = 65.010071mhz, a in = -1dbfs) max1217 toc11 f sample (mhz) sfdr/(-thd) (dbc) 20 50 80 65 35 95 110 125 -thd sfdr snr/sinad, sfdr vs. temperature (f in = 10mhz, a in = -1dbfs) max1217toc12 temperature ( c) snr/sinad, sfdr (db, dbc) 84 88 80 76 72 68 64 -40 -15 10 35 60 85 sfdr snr and sinad -125.0 -100.2 -50.7 -75.5 -26.0 -1.2 imd fft plot max1217 toc13 log magnitude (dbfs) -7dbfs per tone frequency imd = -90dbc f in2 = 100mhz f in1 = 97mhz 2f in2 - f in1 2f in1 - f in2 integral nonlinearity vs. digital output code max1217 toc16 digital output code inl (lsb) 3584 3072 2048 2560 1024 1536 512 0.6 0.3 0 -0.6 -0.3 0.9 -0.9 0 4095 f in = 10mhz -125 -100 -50 -75 -25 0 fft plot max1217 toc14 amplitude (dbfs) -7dbfs per tone frequency imd = -92dbc f in1 = 29mhz 2f in1 - f in2 2f in2 - f in1 f in2 = 31mhz differential nonlinearity vs. digital output code max1217 toc15 digital output code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 0.7 0.4 0.1 -0.5 -0.2 1.0 -0.8 0 4095 f in = 10mhz 34 42 38 54 50 46 66 62 58 70 -30 -20 -25 -15 -10 -5 0 snr/sinad vs. analog input amplitude (f sample = 125mhz, f in = 65.010071mhz) max1217 toc17 analog input amplitude (dbfs) snr/sinad (db) snr sinad -110 -100 -105 -95 -90 -85 -80 -30 -25 -20 -15 -10 -5 0 max1217 toc18 analog input amplitude (dbfs) -75 -70 -65 -60 -55 -50 hd2/hd3 vs. analog input amplitude (f sample = 125mhz, f in = 65.010071mhz) hd2/hd3 (dbc) hd3 hd2
max1217 typical operating characteristics (continued) (av cc = ov cc = +1.8v, f sample = 125mhz, differential input and differential sine-wave clock, 0.1? capacitors on refa and refb, digital output differential r l = 100 , t a = +25?, unless otherwise noted.) 1.8v, dual, 12-bit, 125msps adc for broadband applications _______________________________________________________________________________________ 7 50 55 60 65 70 75 80 85 90 -30 -20 -25 -15 -10 -5 0 sfdr/(-thd) vs. analog input amplitude (f sample = 125mhz, f in = 65.010071mhz) max1217 toc19 analog input amplitude (dbfs) sfdr/(-thd) (dbc) sfdr -thd 58 64 62 60 66 68 70 -5 -1 -2 -4-3 012345 snr/sinad vs. % fs adjustment (f sample = 125mhz, f in = 12.5mhz, a in = -1dbfs) max1217 toc20 full-scale adjustment (%) snr/sinad (db) snr sinad -110 -100 -105 -90 -95 -80 -85 -75 -65 -70 -60 -5 -3 -2 -1 -4 012 4 35 hd2/hd3 vs. % fs adjustment (f sample = 125mhz, f in = 12.5mhz, a in = -1dbfs) max1217 toc21 full-scale adjustment (%) hd2/hd3 (dbc) hd2 hd3 50 60 55 70 65 80 75 85 95 90 100 -5 -3 -2 -1 -4 0 1 2 4 35 sfdr/(-thd) vs. % fs adjustment (f sample = 125mhz, f in = 12.5mhz, a in = -1dbfs) max1217 toc22 full-scale adjustment (%) sfdr/(-thd) (dbc) sfdr -thd 1.14 1.18 1.16 1.22 1.20 1.26 1.24 1.28 1.32 1.30 1.34 0 200 300 100 400 500 600 800 700 900 1000 fs voltage vs. adjust resistor max1217 toc23 fs adjust resistor (k ) v fs (v) resistor value applied between refadja/refadjb and refa/refb increases v fs resistor value applied between refadja/refadjb and agnd decreases v fs
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 8 _______________________________________________________________________________________ pin description pin name function 1 refa channel a reference input/output. channel a 1.24v reference output when refadja is driven low. channel a external reference input when refadja is driven high. connect a 0.1? capacitor from refa to agnd with both external and internal references. 2 refadja channel a reference adjust input. refadja allows for full-scale range adjustments by placing a resistor or trim potentiometer between refadja and agnd (decreases fs range) or refadja and refa (increases fs range). connect refadja to av cc to overdrive the internal reference with an external reference. connect refadja to agnd to allow the internal reference to determine the full-scale range of the data converter. see the fsr adjustments using the internal bandgap reference section. 3, 5, 8, 11, 14, 18, 21, 23, 26, 28, 30, 33, 93, 96, 99, 100 agnd analog converter ground 4, 9, 10, 15, 16, 17, 22, 27, 29, 31, 94, 95 av cc analog supply voltage. bypass av cc to agnd with a 0.1? capacitor for best decoupling results. use additional board decoupling. see the grounding, bypassing, and layout considerations section. 6 inap positive analog input a. positive analog input to channel a. 7 inan negative analog input a. negative analog input to channel a. 12 clkp true clock input. apply an lvds-compatible input level to clkp. 13 clkn complementary clock input. apply an lvds-compatible input level to clkn. 19 inbn negative analog input b. negative analog input to channel b. 20 inbp positive analog input b. positive analog input to channel b. 24 refadjb channel b reference adjust input. refadjb allows for full-scale range adjustments by placing a resistor or trim potentiometer between refadjb and agnd (decreases fs range) or refadjb and refa (increases fs range). connect refadjb to av cc to overdrive the internal reference with an external reference. connect refadjb to agnd to allow the internal reference to determine the full-scale range of the data converter. see the fsr adjustments using the internal bandgap reference section. 25 refb channel b reference input/output. channel b 1.24v reference output when refadjb is driven low. channel b external reference input when refadjb is driven high. connect a 0.1? capacitor from refb to agnd with both external and internal references. 32 clkdiv clock-divider input. clkdiv controls the sampling frequency relative to the input clock frequency. clkdiv has an internal pulldown resistor. clkdiv = 0: sampling frequency is one-half the input clock frequency. clkdiv = 1: sampling frequency is equal to the input clock frequency. 34, 62, 92 ov cc output stage supply voltage. bypass ov cc with a 0.1? capacitor to agnd. use additional board decoupling. see the grounding, bypassing, and layout considerations section. 35 orbp channel b true differential over-range output 36 orbn channel b complementary differential over-range output 37 db11p channel b true differential digital output bit 11 (msb) 38 db11n channel b complementary differential digital output bit 11 (msb) 39 db10p channel b true differential digital output bit 10 40 db10n channel b complementary differential digital output bit 10 41 db9p channel b true differential digital output bit 9 42 db9n channel b complementary differential digital output bit 9
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications _______________________________________________________________________________________ 9 pin description (continued) pin name function 43 db8p channel b true differential digital output bit 8 44 db8n channel b complementary differential digital output bit 8 45 db7p channel b true differential digital output bit 7 46 db7n channel b complementary differential digital output bit 7 47 db6p channel b true differential digital output bit 6 48 db6n channel b complementary differential digital output bit 6 49 db5p channel b true differential digital output bit 5 50 db5n channel b complementary differential digital output bit 5 51 db4p channel b true differential digital output bit 4 52 db4n channel b complementary differential digital output bit 4 53 db3p channel b true differential digital output bit 3 54 db3n channel b complementary differential digital output bit 3 55 db2p channel b true differential digital output bit 2 56 db2n channel b complementary differential digital output bit 2 57 db1p channel b true differential digital output bit 1 58 db1n channel b complementary differential digital output bit 1 59 db0p channel b true differential digital output bit 0 (lsb) 60 db0n channel b complementary differential digital output bit 0 (lsb) 61, 63 ognd output stage ground. ground connection for output circuitry. 64 dcon c om p l em entar y lv d s d i g i tal c l ock o utp ut. outp uts sam e fr eq uency as ad c sam p l i ng fr eq uency. 65 dcop true lvds digital clock output. outputs same frequency as adc sampling frequency. 66 da0n channel a complementary differential digital output bit 0 (lsb) 67 da0p channel a true differential digital output bit 0 (lsb) 68 da1n channel a complementary differential digital output bit 1 69 da1p channel a true differential digital output bit 1 70 da2n channel a complementary differential digital output bit 2 71 da2p channel a true differential digital output bit 2 72 da3n channel a complementary differential digital output bit 3 73 da3p channel a true differential digital output bit 3 74 da4n channel a complementary differential digital output bit 4 75 da4p channel a true differential digital output bit 4 76 da5n channel a complementary differential digital output bit 5 77 da5p channel a true differential digital output bit 5 78 da6n channel a complementary differential digital output bit 6 79 da6p channel a true differential digital output bit 6 80 da7n channel a complementary differential digital output bit 7 81 da7p channel a true differential digital output bit 7 82 da8n channel a complementary differential digital output bit 8 83 da8p channel a true differential digital output bit 8 84 da9n channel a complementary differential digital output bit 9
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 10 ______________________________________________________________________________________ pin description (continued) pin name function 85 da9p channel a true differential digital output bit 9 86 da10n channel a complementary differential digital output bit 10 87 da10p channel a true differential digital output bit 10 88 da11n channel a complementary differential digital output bit 11 (msb) 89 da11p channel a true differential digital output bit 11 (msb) 90 oran channel b complementary differential over-range output 91 orap channel b true differential over-range output 97 t /bb output format select input for channel b. t /bb controls the digital output format of channel b of the max1217. t /bb has an internal pulldown resistor. t /bb = 1: binary output format. t /bb = 0: two?-complement output format. 98 t /ba output format select input for channel a. t /ba controls the digital output format of channel a of the max1217. t /ba has an internal pulldown resistor. t /ba = 1: binary output format. t /ba = 0: two?-complement output format. ?p exposed paddle. the exposed paddle is located on the backside of the device and must be connected to agnd. max1217 1k 1k inap inan ognd agnd av cc ov cc t/h reference lvds data port div1/div2 clock management orbp/orbn db0_?b11_ da0_?a11_ orap/oran clkdiv cklp ckln 12-bit pipeline adc channel a 1k 1k inbp inbn t/h 12-bit pipeline adc channel b t/ba/b refadja refa refb refadjb dcop dcon figure 1. functional diagram
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ______________________________________________________________________________________ 11 detailed description theory of operation the max1217 uses a fully differential pipelined archi- tecture that allows for high-speed conversion, opti- mized accuracy, and linearity while minimizing power consumption. both positive inputs (inap, inbp) and negative/comple- mentary analog inputs (inan, inbn) are centered around a 0.8v common-mode voltage, and each accept a ? fs / 4 differential analog input voltage swing, providing a 1.475v p-p typical differential full- scale signal swing. each set of inputs (inap, inan and inbp, inbn) is sampled when the differential sampling clock signal transitions high. when using the clock- divide mode, the analog inputs are sampled at every other high transition of the differential sampling clock. each pipeline converter stage converts its input voltage to a digital output code. at every stage, except the last, the error between the input voltage and the digital out- put code is multiplied and passed along to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. the result is a 12-bit parallel digital output word in selectable two?-complement or offset binary output formats with lvds-compatible out- put levels (figure 1). analog inputs the max1217 features two sets of fully differential inputs (inap, inan and inbp, inbn) for each input channel. differential inputs feature good rejection of even-order harmonics, which allows for enhanced ac performance as the signals are progressing through the analog stages. the max1217 analog inputs are self-biased at a 0.8v common-mode voltage and allow a 1.475v p-p differential input voltage swing (figure 2). both sets of inputs are self-biased through 1k resis- tors, resulting in a typical 2k differential input resis- tance. drive the analog inputs of the max1217 in ac-coupled configuration to achieve best dynamic per- formance. see the transformer-coupled, differential analog input drive section. on-chip reference circuit the max1217 features an internal 1.24v bandgap ref- erence circuit (figure 3), which, in combination with two internal reference-scaling amplifiers, determines the fsr of each channel. bypass refa and refb with a 0.1? capacitor to agnd. adjust the voltage of the bandgap reference for each channel independently by adding an external resistor (e.g., 100k trim poten- tiometer) between refadja/refadjb and agnd or refadja/refadjb and refa/refb to compensate for gain errors or increase the fsr of each channel. see the applications information section for a detailed description of this process. to disable the internal reference for each channel, con- nect the reference adjust input (refadja, refadjb) to av cc . apply an external, stable reference to the channel? reference input/output (refa, refb) to set the converter? full scale. to enable the internal refer- ence for a channel, connect the appropriate reference adjust input (refadja, refadjb) to agnd. clock inputs (clkp, clkn) drive the clock inputs of the max1217 with an lvds- compatible clock to achieve the best dynamic perfor- mance. the clock signal source must be a high-quality, low phase noise to avoid any degradation in the noise performance of the adc. the clock inputs (clkp, clkn) are internally biased to 1.15v to accept a typical 0.5v p-p differential signal swing (figure 4). see the differential, ac-coupled lvpecl-compatible clock input section for more circuit details on how to drive clkp and clkn appropriately. although not recom- mended, the clock inputs also accept a single-ended input signal. the max1217 also features an internal clock-manage- ment circuit (duty-cycle equalizer) to ensure that the clock signal applied to inputs clkp and clkn is processed to provide a 50% duty-cycle clock signal that desensitizes the performance of the converter to varia- tions in the duty cycle of the input clock source. the clock duty-cycle equalizer cannot be turned off exter- nally and requires a minimum 40mhz clock frequency to allow the device to meet data sheet specifications. if the max1217 is not clocked, the digital outputs begin to change state randomly, resulting in a supply current increase of up to 40ma. clock outputs (dcon, dcop) the max1217 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. additionally, the clock output can be used to synchronize external devices (e.g., fpgas) to the adc. dcop and dcon are differential outputs with lvds-compatible voltage levels. there is a 5.2ns (typ) delay between the rising (falling) edge of clkp (clkn) and the rising (falling) edge of dcop (dcon). see figure 5 for timing details. divide-by-2 clock control the max1217 offers a clock control line (clkdiv) that supports the reduction of clock jitter in a system. connect clkdiv to ognd to enable the adc? internal
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 12 ______________________________________________________________________________________ divide-by-2 clock divider. data is now updated at one- half the adc? input clock rate. clkdiv has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. connecting clkdiv to ov cc disables the divide-by-2 mode. 1k 1k in_p in_n 12-bit pipeline adc c s c s c p c p to common mode from clock-management block av cc max1217 t/h c s is the sampling capacitance c p is the parasitic capacitance ~ 1pf in_p in_n in_p - in_n v cm v cm + v fs / 4 v cm - v fs / 4 +v fs / 2 -v fs / 2 gnd gnd 1.4v differential fsr figure 2. simplified analog input architecture and allowable input voltage range
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ______________________________________________________________________________________ 13 system timing requirements figure 5 depicts the relationship between the clock input and output, analog input, sampling event, and data output. the max1217 samples on the rising (falling) edge of clkp (clkn). output data is valid on the next rising (falling) edge of dcop (dcon), with an internal latency of 11 clock cycles. digital outputs (da0p/n?a11p/n, db0p/n?b11p/n, orap/n, orbp/n, dcop/n) and control inputs t/ ba, t /bb digital outputs da0p/n?a11p/n, db0p/n?b11p/n, orap/n, orbp/n, and dcop/n are lvds compatible, and data on da0p/n?a11p/n and db0p/n?b11p/n are presented in either binary or two?-complement for- mat (table 1). the t /ba, t /bb control lines are lvcmos- compatible inputs that allow a selectable output format for each channel. pulling t /ba, t /bb low outputs data in two? complement and pulling it high presents data in offset binary format on each of the channels?12-bit par- allel buses. t /ba, t /bb have an internal pulldown resis- tor and can be left unconnected in applications using *refadja/b can be shorted to agnd through a 1k resistor or potentiometer. reft_: top of reference ladder refb_: bottom of reference ladder reference buffer channel b full scale = reftb - refbb av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refb refadjb* 0.1 f reftb refbb reference buffer channel a full scale = refta - refba av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refa refadja* 0.1 f refta refba 1v max1217 figure 3. simplified reference architecture
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 14 ______________________________________________________________________________________ only two?-complement output format. all lvds outputs provide a typical 0.371v voltage swing around roughly a 1.2v common-mode voltage, and must be terminated at the far end of each transmission line pair (true and com- plementary) with 100 . apply a 1.71v to 1.89v voltage supply at ov cc to power the lvds outputs. the max1217 offers an additional set of differential out- put pairs (orap/n and orbp/n) to flag out-of-range conditions for each channel, where out-of-range is above positive or below negative full scale. an out-of- range condition on each channel is identified with orap or orbp (oran or orbn) transitioning high (low). note: although a differential lvds output architecture reduces single-ended transients to the supply and ground planes, capacitive loading on the digital out- puts should still be kept as low as possible. using lvds buffers on the digital outputs of the adc when driving larger loads improves overall performance and reduces system-timing constraints. applications information fsr adjustments using the internal bandgap reference the max1217 supports a 10% (?%) full-scale adjust- ment range on each channel. add an external resistor ranging from 13k to 1m between the reference adjust input of the channel (refadja, refadjb) and agnd to decrease the full-scale range of the channel. adding a variable resistor, potentiometer, or predeter- mined resistor value between the reference adjust input of a channel (refadja, refadjb) and its respective reference input/output (refa, refb) increases the fsr of the channel. figure 6a shows the two possible con- figurations and their impact on the overall full-scale range adjustment of the max1217. the fsr for each channel can be set to any value in the allowed range independent of the fsr of the other channel. do not use resistor values of less than 13k to avoid instability of the internal gain regulation loop for the bandgap ref- erence. see figure 6b for the resulting fsr for a series of resistor values. differential, ac-coupled, lvpecl- compatible clock input 5.35k 5.35k 5.35k 2.89k av dd agnd clkp clkn figure 4. simplified clock input architecture t pdl t cpdl t latency clkn clkp dcop dcon n + 1 n + 11 n + 12 n + 1 n + 1 n - 10 n - 11 n n n t ad sampling event sampling event sampling event sampling event sampling event inan/inbn inap/inbp t cl t ch n - 11 n - 10 n - 1 da0p/n?a11p/n db0p/n?b11p/n figure 5. system and output timing diagram
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ______________________________________________________________________________________ 15 the max1217 dynamic performance depends on the use of a very clean clock source. the phase noise floor of the clock source has a negative impact on the snr performance. spurious signals on the clock signal source also affect the adc? dynamic range. the pre- ferred method of clocking the max1217 is differentially with lvds- or lvpecl-compatible input levels. the fast data transition rates of these logic families minimize the clock input circuitry? transition uncertainty, thus improving the snr performance. to accomplish this, ac-couple a 50 reverse-terminated clock signal source with low phase noise into a fast differential receiver, such as the max9388 (figure 7). the receiver produces the necessary lvpecl output levels to drive the clock inputs of the data converter. transformer-coupled, differential analog input drive the max1217 provides the best sfdr and thd perfor- mance with fully differential input signals. in differential input mode, even-order harmonics are lower since the inputs to each channel (inap/n and inbp/n) are balanced, and each of the channel? inputs only requires half the signal swing compared to a single-ended configuration. wideband rf transformers provide an excellent solu- tion to convert a single-ended signal to a fully differen- tial signal. apply a secondary-side termination to a 1:1 transformer (e.g., mini-circuit? adt1-1wt) by two sep- arate 24.9 resistors. higher source impedance values can be used at the expense of a degradation in dynam- ic performance. use resistors with tight tolerance (0.5%) to minimize effects of imbalance, maximizing the adc? dynamic range. this configuration optimizes thd and sfdr performance of the adc by reducing the effects of transformer parasitics. however, the source impedance combined with the shunt capaci- tance provided by a pc board and the adc? parasitic capacitance limit the adc? full-power input bandwidth. to further enhance thd and sfdr performance at high input frequencies (> 100mhz) place a second trans- former (figure 8) in series with the single-ended-to-differ- ential conversion transformer. the second transformer reduces the increase of even-order harmonics at high frequencies. single-ended, ac-coupled analog inputs although not recommended, the max1217 can be used in single-ended mode (figure 9). ac-couple the analog signals to the positive input of each channel (inap, inbp) through a 0.1? capacitor terminated with a 49.9 resistor to agnd. terminate the negative input of each channel (inan, inbn) with a 24.9 resistor in series with a 0.1? capacitor to agnd. in single-ended mode the input range is limited to approximately half of the fsr of the device, and dynamic performance usually degrades. grounding, bypassing, and board layout the max1217 requires board layout design techniques suitable for high-speed data converters. this adc accepts separate analog and output power supplies. the analog and output power-supply inputs accept 1.71v to 1.89v input voltage ranges. although both av cc and ov cc can be supplied from one source, use sepa- rate sources to reduce performance degradation caused table 1. max1217 digital output coding inap/inbp analog input voltage level inan/inbn analog input voltage level out-of-range orap/orbp (oran/orbn) binary digital output code (da11p/n?a0p/n; db11p/n?b0p/n) two?-complement digital output code (da11p/n?a0p/n; db11p/n?b0p/n) > v cm + v fs /4 < v cm - v fs /4 1 (0) 1111 1111 1111 (exceeds +fs, or set) 0111 1111 1111 (exceeds +fs, or set) v cm + v fs /4 v cm - v fs /4 0 (1) 1111 1111 1111 (+fs) 0111 1111 1111 (+fs) v cm v cm 0 (1) 1000 0000 0000 or 0111 1111 1111 (fs / 2) 0000 0000 0000 or 1111 1111 1111 (fs / 2) v cm - v fs /4 v cm + v fs /4 0 (1) 0000 0000 0000 (-fs) 1000 0000 0000 (-fs) < v cm + v fs /4 > v cm - v fs /4 1 (0) 0000 0000 0000 (exceeds -fs, or set) 1000 0000 0000 (exceeds -fs, or set)
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 16 ______________________________________________________________________________________ by output switching currents, which can couple into the analog supply network. isolate analog and output sup- plies (av cc and ov cc ) where they enter the pc board with separate networks of ferrite beads and capacitors to their corresponding grounds (agnd, ognd). to achieve optimum performance, provide each supply with a separate network of 47? tantalum capacitor and parallel combination of 10? and 1? ceramic capaci- tors. additionally, the adc requires each supply input to be bypassed with a separate 0.1? ceramic capaci- tor (figure 10). locate these capacitors directly at the adc supply inputs or as close as possible to the max1217. choose surface-mount capacitors, whose preferred location is on the same side as the converter to save space and minimize inductance. if close place- ment on the same side is not possible, route these bypassing capacitors through vias to the bottom side of the pc board. multilayer boards with separate ground and power planes produce the highest level of signal integrity. use a split ground plane arranged to match the physical location of the analog and output grounds on the adc? package. join the two ground planes at a single point so the noisy output ground currents do not interfere with the analog ground plane. dynamic currents travel- ing long distances before reaching ground cause large and undesirable ground loops. ground loops can degrade the input noise by coupling back to the analog front-end of the converter, resulting in increased spurious activity, leading to decreased noise performance. all agnd connections could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, output systems ground. to minimize the cou- pling of the output signals from the analog input, segre- gate the output bus carefully from the analog input circuitry. to further minimize the effects of output noise coupling, position ground return vias throughout the lay- out to divert output switching currents away from the sensitive analog sections of the adc. this approach does not require split ground planes, but can be accom- max1217 reference buffer adc full scale = refta/b - refba/b 1v av cc av cc / 2 av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refa/b refadja/b refa/b refadja/b 13k to 1m 0.1 f refta/b refba/b max1217 reference buffer adc full scale = refta/b - refba/b 1v g control line to disable reference buffer reference- scaling amplifier 0.1 f 13k to 1m refta/b refba/b figure 6a. circuit suggestions to adjust the adc? full-scale range 1.14 1.18 1.16 1.22 1.20 1.26 1.24 1.28 1.32 1.30 1.34 0 200 300 100 400 500 600 800 700 900 1000 fs voltage vs. adjust resistor fs adjust resistor (k ) v fs (v) resistor value applied between refadja/refadjb and refa/refb increases v fs resistor value applied between refadja/refadjb and agnd decreases v fs figure 6b. fs adjustment range vs. fs adjustment resistor
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ______________________________________________________________________________________ 17 plished by placing substantial ground connections between the analog front-end and the digital outputs. the max1217 is packaged in a 100-pin tqfp-ep pack- age ( package code: c100e-6 ), providing greater design flexibility, increased thermal dissipation, and optimized ac performance of the adc. the exposed paddle (ep) must be soldered to agnd. the data converter die is attached to an ep lead frame with the back of this frame exposed to the package bottom surface, facing the pc board side of the pack- age. this allows a solid attachment of the package to the board with standard infrared (ir) flow soldering techniques. 0.1 f 0.1 f 0.1 f 0.1 f single-ended input terminal 50 50 clkn clkp 8 18 1 19 12 10 14 16 15 9 510 50 510 v clk 0.1 f max9388 inap/inbp inan/inbn agnd av cc ov cc max1217 db0p/n?b11p/n, orbp/n 12 da0p/n?a11p/n, orap/n 12 ognd 50 figure 7. differential, ac-coupled, lvpecl-compatible clock input configuration 24.9 24.9 0.1 f adt1-1wt adt1-1wt 10 10 single-ended input terminal 0.1 f 0.1 f inap/inbp inan/inbn agnd av cc ov cc max1217 db0p/n?b11p/n, orbp/n 12 da0p/n?a11p/n, orap/n 12 ognd figure 8. analog input configuration with back-to-back transformers and secondary-side termination
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 18 ______________________________________________________________________________________ thermal efficiency is one of the factors for selecting a package with an exposed paddle for the max1217. the exposed paddle improves thermal efficiency and ensures a solid ground connection between the adc and the pc board? analog ground layer. route the digital output traces for a high-speed, high- resolution data converter with care. keep trace lengths at a minimum and place minimal capacitive loading, less than 5pf, on any digital trace to prevent coupling to sensitive analog sections of the adc. run the lvds output traces as differential lines with 100 characteris- tic impedance from the adc to the lvds load device. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. however, the static linearity parameters for the max1217 are measured using the histogram method with a 10mhz input frequency. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl agnd note: each power-supply pin (analog, output) should be decoupled with an individual 0.1 f capacitor close to the adc. bypassing?dc level bypassing?oard level analog power- supply source 1 f 10 f47 f av cc ov cc max1217 av cc db0p/n?b11p/n, orbp/n 12 da0p/n?a11p/n, orap/n 12 ognd 0.1 f 0.1 f output-driver power-supply source 1 f 10 f47 f ov cc figure 10. grounding, bypassing, and decoupling recommendations for the max1217 inap/inbp 49.9 24.9 inan/inbn 0.1 f single-ended input terminal 0.1 f agnd av cc ov cc max1217 db0p/n?b11p/n, orbp/n 12 da0p/n?a11p/n, orap/n 12 ognd figure 9. single-ended ac-coupled analog input configuration
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ______________________________________________________________________________________ 19 error specification that is -1 lsb or better, guarantees no missing codes and a monotonic transfer function. the max1217? dnl specification is measured with the histogram method based on a 10mhz input tone. dynamic parameter definitions aperture jitter figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 11). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db [max] = 6.02db x n + 1.76db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first six harmonics (hd2?d7), and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components excluding the fundamen- tal and the dc offset. in the case of the max1217, sinad is computed from a curve fit. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the funda- mental (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent, excluding dc offset. sfdr is usually measured in dbc with respect to the fundamental (carrier) frequency amplitude or in dbfs with respect to the adc? full- scale range. intermodulation distortion (imd) imd is the ratio of the rms sum of the intermodulation products to the rms sum of the two fundamental input tones. this is expressed as: the fundamental input tone amplitudes (v 1 and v 2 ) are at -7dbfs. the intermodulation products are the amplitudes of the output spectrum at the following frequencies: 2nd-order intermodulation products (im2): f in1 + f in2 , f in2 - f in1 3rd-order intermodulation products (im3): 2f in1 - f in2 , 2f in2 - f in1 , 2f in1 + f in2 , 2f in2 + f in1 4th-order intermodulation products (im4): 3f in1 - f in2 , 3f in2 - f in1 , 3f in1 + f in2 , 3f in2 + f in1 5th-order intermodulation products (im5): 3f in1 - 2f in2 , 3f in2 - 2f in1 , 3f in1 + 2f in2 , 3f in2 + 2f in1 full-power bandwidth a large -1dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. the -3db point is defined as the full-power input bandwidth frequency of the adc. offset error ideally, the midscale max1217 transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. gain error ideally, the positive full-scale max1217 transition occurs at 1.5 lsb below positive full scale, and the negative full-scale transition occurs at 0.5 lsb above negative full scale. the gain error is the difference of the measured transition points minus the difference of the ideal transition points. imd vv v vv im im imn log ... = +++ + ? ? ? ? ? ? ? ? 20 2 1 2 2 2 1 2 2 2 hold analog input sampled data (t/h) t/h t ad t aj track track clkp clkn figure 11. aperture jitter/delay specifications
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications 20 ______________________________________________________________________________________ effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 7 are the amplitudes of the 2nd- through 7th-order harmonics (hd2?d7). thd log = ? ? ? ? ? ? ? ? 20 (v +v +v +v +v +v ) v 2 2 3 2 4 2 5 2 6 2 7 2 1 enob sinad = ? ? ? ? ? ? ? 176 602 . .
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications ______________________________________________________________________________________ 21 pin configuration top view 1 refa 2 refadja 3 agnd 4 av cc 5 agnd 6 inap 7 inan 8 agnd 9 av cc 10 av cc 11 agnd 12 13 14 agnd 15 av cc 16 av cc 17 av cc 18 agnd 19 inbn 20 inbp 21 agnd 22 av cc 23 agnd 24 refadjb 25 refb 75 da4p 74 da4n 73 da3p 72 da3n 71 da2p 70 da2n 69 da1p 68 da1n 67 da0p 66 da0n 65 dcop 64 dcon 63 ognd 62 ov cc 61 ognd 60 db0n 59 db0p 58 db1n 57 db1p 56 db2n 55 db2p 54 db3n 53 db3p 52 db4n 51 db4p 26 agnd 27 av cc 28 agnd 29 av cc 30 agnd 31 av cc 32 clkdiv 33 agnd 34 ov cc 35 orbp 36 orbn 37 db11p 38 db11n 39 db10p 40 db10n 41 db9p 42 db9n 43 db8p 44 db8n 45 db7p 46 db7n 47 db6p 48 db6n 49 db5p 50 db5n 100 agnd 99 agnd 98 97 96 agnd 95 av cc 94 av cc 93 agnd 92 ov cc 91 orap 90 oran 89 da11p 88 da11n 87 da10p 86 da10n 85 da9p 84 da9n 83 da8p 82 da8n 81 da7p 80 da7n 79 da6p 78 da6n 77 da5p 76 da5n clkp clkn tqfp t/ba t/bb max1217 exposed paddle
max1217 1.8v, dual, 12-bit, 125msps adc for broadband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 14x14x1.00l tqpf, exp. pad.eps package outline, 100l tqfp 21-0116 2 1 c 14x14x1.00mm with exposed pad option package outline, 100l tqfp 21-0116 2 2 c 14x14x1.00mm with exposed pad option springer
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max1217 part number table notes: see the max1217 quickview data sheet for further information on this product family or download the max1217 full data sheet (pdf, 336kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max1217ec q+d tqfp;100 pin;14x14x1.0mm dwg: 21-0116d (pdf) use pkgcode/variation: c 100e+6 * -40c to +85c rohs/lead-free: yes materials analysis max1217ec q+td tqfp;100 pin;14x14x1.0mm dwg: 21-0116d (pdf) use pkgcode/variation: c 100e+6 * -40c to +85c rohs/lead-free: yes materials analysis max1217ec q-d tqfp;100 pin;14x14x1mm dwg: 21-0116d (pdf) use pkgcode/variation: c 100e-6 * -40c to +85c rohs/lead-free: no materials analysis max1217ec q-td tqfp;100 pin;14x14x1mm dwg: 21-0116d (pdf) use pkgcode/variation: c 100e-6 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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